A parallel to serial conversion circuit is necessary for transmission of parallel data via a serial interface. A circuit diagram of conventional parallel to serial conversion circuit is shown in FIG. 1. The conventional parallel to serial conversion circuit includes a data conversion circuit 10 and a phase locked loop circuit 12, as shown in FIG. 1. The phase locked loop circuit 12 is operable to multiply the frequency of an inputted source clock to obtain a multiplied clock for the data conversion. The data conversion circuit 10 is operable to receive parallel data in synchronization with a parallel clock (e.g. a parallel transmission clock), convert the received parallel data into serial data in response to the multiplied clock from the phase locked loop circuit 12, and output the serial data in synchronization with a serial clock (e.g. a serial transmission clock). In the conventional parallel to serial conversion circuit, the phase locked loop circuit operates even if the parallel data to be transmitted is not inputted. In other words, the phase locked loop circuit oscillates at a frequency of free oscillation even if the inputted source clock to be multiplied is interrupted. Therefore, the phase locked loop circuit consumes a current of about several hundreds of μA even when the parallel data to be transmitted is not inputted.
A parallel to serial conversion device is disclosed in U.S. Pat. No. 6,771,194 entitled “Parallel to serial conversion device and method”, as shown in FIG. 2, and the parallel to serial conversion device includes a plurality of current sources 10, 12, 14 and 16, a plurality of selecting means 18, 20, 22 and 24, a current steering means 26, and a voltage outputting means 28. The number of the current sources 10, 12, 14 and 16 and the number of the selecting means 18, 20, 22 and 24 correspond to the number of data bits of the parallel data being converted into the serial data. In the disclosure of U.S. Pat. No. 6,771,194, because only one bit of the parallel data is being converted at one time, clock signals ck1, ck2, ck3 and ck4 of the selecting means 18, 20, 22 and 24 are used to determine which of the selecting means 18, 20, 22 and 24 is in an active state (i.e. converting the data bit). For example, if the selecting means 18 is in the active state, the selecting means 18 and the corresponding current source 10 are provided with a first current I0, while the other selecting means 20, 22 and 24 are provided with no current. Further, a second current (n−1)*I0 is directed towards the current steering means 26, which in turn divides the second current (n−1)*I0 and directs the divided second current (n−1)*I0 to the selecting means 20, 22 and 24 respectively. Thus, only a current of n*I0 is used for all tail currents, thereby reducing greatly the current consumption. In the disclosure of U.S. Pat. No. 6,771,194, the selecting means correspond to a clock signal with the highest frequency. In other words, if the clock frequency of the parallel data is f0 and the number of bits of the parallel data is n, the clock signal corresponding to the selecting means has a frequency of f=n*f0. For example, if the clock frequency of the parallel data is 100 MHz and the number of bits of the parallel data is 10, the clock signal corresponding to the selecting means has a frequency of 100 MHZ*10=1 GHz. The clock signal with such a high frequency is difficult to obtain, has a high requirement on the system and requires additionally a frequency multiplying means, as a result, the complexity of the system is increased. If the teachings of U.S. Pat. No. 6,771,194 are applied in a low frequency environment, the power consumption may be reduced, because the current consumption in the system is relatively low for some time due to signal switching. However, if the teachings of U.S. Pat. No. 6,771,194 is applied in a high frequency environment, due to the frequent signal switching, the system operates at a low current for a very short of time which may be ignored, and the system may be regarded as active all the time, thus the reduction of power consumption is insignificant.
In addition, U.S. Pat. No. 6,741,193 discloses a parallel in serial out circuit having flip-flop latching at multiple clock rates, and the parallel in serial out circuit may convert data bits of the parallel data into corresponding serial data by means of frequency division and multiple groups of flip-flop latching at various frequencies, for example, in an embodiment of U.S. Pat. No. 6,741,193, a frequency of 400 MHz is divided into frequencies of 50 MHz, 100 MHz, 200 MHz and 400 MHz. In the disclosures of U.S. Pat. No. 6,741,193, the highest frequency needs to be divided and the flip-flop latching at various frequencies is required. The increase in the data bits increases the frequency division times and the required flip-flop latches, which increases the system complexity and increase the power consumption for the frequency division, but fails to ensure accurate frequency division.